Bug Check 0x3E

The MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED bug check shows that one processor differs too much from others.

Bug Check Code	MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED
1st Argument	0x10 for difference in PGE support; 0x40 for difference in MTRR support; 0x80 for difference in CX8 support; 0x0387 for difference in whether numerical coprocessor is present; 0x0400 for difference in PAT support; 0x0800 for difference in FXSR support or value of MXCSR; 0x2000 for difference in SSE support; 0x00040000 for difference in CLFSH support; 0x20000000 for difference in Execute-Disable support
2nd Argument	zero, in general; expected MXCSR value, if difference is in value of MXCSR
3rd Argument	zero, in general; rejected MXCSR value, if different is in value of MXCSR
4th Argument	zero

Windows has long been documented as being executable on multiple processors only on symmetric multiprocessor (SMP) systems. This is often expressed as meaning that all processors must be identical. However, for many processor features, the kernel explicitly tolerates differences by the simple expedient of working to the lowest capability. If such a feature is not supported on all processors, it simply doesn’t get used for any.

For some features, differences among the processors are explicitly rejected. The usual case is that the boot processor’s support for the feature, or lack of support, is already relied on by the time the kernel starts other processors, such that reconfiguring for a difference would be impossible, difficult or too much trouble.

The following features must either be supported by all processors or be supported by none:

the FXSAVE and FXRSTOR instructions, as indicated by the FXSR bit (0x01000000) in the CPUID feature flags;
Streaming SIMD Extensions (SSE), as indicated by the SSE bit (0x02000000) in the CPUID feature flags.

Similarly, each processor must have its own numeric coprocessor, else none may.

For the following features, if the boot processor supports the feature, then so must all other processors:

the CMPXCHG8B instruction, as indicated (typically) by the CX8 bit (0x0100) in the CPUID feature flags;
global pages, as indicated by the PGE bit (0x2000) in the CPUID feature flags;
Page Attribute Table, as indicated by the PAT bit (0x00010000) in the CPUID feature flags;
Memory Type Range Registers, as indicated by the MTRR bit (0x1000) in the CPUID feature flags;
the CLFLUSH instruction, as indicated by the CLFSH bit (0x00080000) in the CPUID feature flags;
Execute-Disable bit in page table entries, as indicated by bit 20 in EDX returned by CPUID function 0x80000001.

Additionally, if the boot processor supports CLFLUSH, then all processors must have the same line size (which CPUID function 1 returns in bits 8 to 15 of EBX).

For FXSR support, the MXCSR register must be consistent across all processors. When inconsistent, the expected and rejected values are given as the 2nd and 3rd arguments.

For MTRR support, the machine-specific register MTRRcap (0xFE) must be consistent across all processors. Inconsistency of the machine-specific register MTRRdefType (0x2FF) is tested but tolerated, albeit with a complaint to the debugger even in the free build:

KiInitializeMTRR: MTRR_MSR_DEFAULT is not consistent between processors.

Documentation Status

Microsoft’s documentation says that there are no parameters for this bug check.